ICASSP 2005 Philadelphia

2005 IEEE International Conference on Acoustics, Speech, and Signal Processing

March 18-23, 2005 • Pennsylvania Convention Center/Marriott Hotel • Philadelphia, PA, USA

DISPS-P2: DSP Implementation II

Session Type: Poster
Time: Monday, March 21, 15:30 - 17:30
Location: CC: Poster 7
Chair: Shurva Bhattacharyya, University of Maryland, College Park
 
DISPS-P2.1: A NEW RECONFIGURABLE BIT-SERIAL SYSTOLIC DIVIDER FOR GF(2^M) AND GF(P).
         Aaron Cohen; University of Minnesota Twin Cities
         Keshab Parhi; University of Minnesota Twin Cities
 
DISPS-P2.2: EFFICIENT IMPLEMENTATION OF A SPECTRUM ANALYZER FOR FIXED POINT ARCHITECTURES
         Antonio Valdessalici; Advanced Industrial Design in Acoustics
         Giacomo Frassi; Advanced Industrial Design in Acoustics
         Alberto Bellini; University of Parma
 
DISPS-P2.3: MULTIPLIERLESS REALIZATION OF BANDPASS AND BANDSTOP DIGITAL FILTERS TRANSFORMED FROM ALL-POLE LOWPASS FILTERS
         Mrinmoy Bhattacharya; Tampere University of Technology
         Tapio Saramäki; Tampere University of Technology
 
DISPS-P2.4: DESIGN OF A FLEXIBLE VLSI ARCHITECTURE FOR M-CHANNEL FILTER BANK LIFTING FACTORIZATIONS
         Ruben Bartholomä; Pforzheim University of Applied Sciences
         Thomas Greiner; Pforzheim University of Applied Sciences
         Frank Kesel; Pforzheim University of Applied Sciences
 
DISPS-P2.5: PIPELINED PARALLEL DECISION FEEDBACK DECODERS (PDFDS) FOR HIGH SPEED ETHERNET OVER COPPER
         Yongru Gu; University of Minnesota
         Keshab Parhi; University of Minnesota
 
DISPS-P2.6: HARDWARE-EFFICIENT DISTRIBUTED ARITHMETIC ARCHITECTURE FOR HIGH-ORDER DIGITAL FILTERS
         Heejong Yoo; Georgia Institute of Technology
         David Anderson; Georgia Institute of Technology
 
DISPS-P2.7: RECONFIGURABLE ARCHITECTURE FOR ULTRASONIC SIGNAL COMPRESSION AND TARGET DETECTION
         Erdal Oruklu; Illinois Institute of Technology
         Guilherme Cardoso; Illinois Institute of Technology
         Jafar Saniie; Illinois Institute of Technology
 
DISPS-P2.8: MODELING IMAGE PROCESSING SYSTEMS WITH HOMOGENEOUS PARAMETERIZED DATAFLOW GRAPHS
         Mainak Sen; University of Maryland
         Shuvra S. Bhattacharyya; University of Maryland, College Park
         Tiehan Lv; Princeton University
         Wayne Wolf; Princeton University
 
DISPS-P2.9: ARITHMETIC COMPLEXITY OF THE SPLIT-RADIX FFT ALGORITHMS
         Saad Bouguezel; Concordia University
         M. Omair Ahmad; Concordia University
         M. N. S. Swamy; Concordia University
 
DISPS-P2.10: A ROUGH PROGRAMMING APPROACH TO POWER-AWARE VLIW INSTRUCTION SCHEDULING FOR DIGITAL SIGNAL PROCESSORS
         Shu Xiao; Nanyang Technological University
         Edmund Lai; Nanyang Technological University
 
DISPS-P2.11: THE EFFECTS OF PIPELINING FEEDBACK LOOPS IN HIGH SPEED DSP SYSTEMS
         Steven Alexander; University of Strathclyde
         Robert Stewart; University of Strathclyde
 
DISPS-P2.12: REAL-TIME DUAL-MICROPHONE SPEECH ENHANCEMENT USING FIELD PROGRAMMABLE GATE ARRAYS
         David Halupka; University of Toronto
         Seyed Alireza Rabi; University of Toronto
         Parham Aarabi; University of Toronto
         Ali Sheikholeslami; University of Toronto
 
DISPS-P2.13: PERFORMANCE ANALYSIS OF THE FILTERED BACKPROJECTION IMAGE RECONSTRUCTION ALGORITHMS
         Thammanit Pipatsrisawat; Carnegie Mellon University
         Aca Gacic; Carnegie Mellon University
         Franz Franchetti; Carnegie Mellon University
         Markus Pueschel; Carnegie Mellon University
         José M. F. Moura; Carnegie Mellon University
 
DISPS-P2.14: SIGNAL MULTIPLEXING AND MODULATION FOR VOLUME CONDUCTION COMMUNICATION
         Paul Roche; University of Pittsburgh
         Mingui Sun; University of Pittsburgh
         Robert Sclabassi; University of Pittsburgh
 
©2018 Conference Management Services, Inc. -||- email: webmaster@icassp2005.com -||- Last updated Friday, August 17, 2012